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What is VIPPO PCB: Via-in-Pad Plated Over Design & Manufacturing Guide
What is vippo? VIPPO PCB means Via-in-Pad Plated Over. The via is placed directly in a component pad, filled, cured, planarized, and plated over to create a flat surface for soldering. This structure can improve fine-pitch BGA escape routing and routing density in HDI or compact multilayer PCBs. It also adds fabrication and assembly controls that must be reviewed before release.
This guide explains the VIPPO structure, when it is useful, how it differs from conventional fanout and other via structures, the design inputs a fabricator needs, common reliability risks, and the questions to ask during a DFM review.
What is VIPPO PCB?
A VIPPO structure places a via inside a component pad and then fills and plates over the via. The finished surface should be sufficiently flat and solderable for the intended assembly process. The objective is to make a direct vertical connection to an inner layer while preserving surface routing space around a fine-pitch component.
VIPPO is often discussed together with via-in-pad, but the manufacturing requirement is more specific: the via cannot simply remain an open hole under the pad. The fill, cure, planarization, copper cap, plating quality, pad geometry, and assembly profile must be controlled as one process chain.
When Should You Use VIPPO?
VIPPO is a design option, not a default requirement. Consider it when:
Fine-pitch BGA escape routing is congested.
The board outline or layer count is constrained.
A direct pad-to-inner-layer connection improves the fanout strategy.
An HDI stackup cannot provide enough routing channels with conventional vias.
A thermal pad or package-specific pad structure requires an integrated via solution.
A conventional fanout may be the better choice when the package pitch is relaxed, routing channels are available, cost sensitivity is high, or the VIPPO process provides little measurable benefit.
VIPPO vs Conventional Fanout
| Factor | VIPPO | Conventional fanout |
|---|---|---|
| Via location | Inside the component pad | Outside the pad, connected by a short trace or dog-bone |
| Surface routing | Reduced around dense pads | More surface breakout space required |
| Fine-pitch BGA | Often advantageous | Can become congested |
| Process complexity | Higher | Lower |
| Cost | Usually higher; confirm by stackup and quantity | Usually lower |
| Main risks | Fill, voiding, planarity, copper cap, solderability | Routing congestion and pad escape |
VIPPO Design Inputs
BGA pitch, pad diameter, solder mask definition, and package drawing
Via finished diameter, capture pad, fill requirement, and copper cap requirement
Layer-to-layer connection and stackup assignment
Board thickness, copper thickness, dielectric thickness, and HDI sequence
Assembly method, component type, solder paste, reflow profile, and inspection method
Electrical targets such as impedance, loss, return path, and power delivery
Reliability requirements including thermal cycling, drop, vibration, or package-level qualification
SLLPCB supports 50 μm-class VIPPO laser microvias with controlled via filling, curing, planarization and copper cap formation. The process provides flat, solderable via-in-pad surfaces for fine-pitch BGA, advanced HDI and high-density package designs, with reliability inspection and validation for demanding assembly applications.
VIPPO Manufacturing Flow
A typical controlled flow includes via formation, cleaning, desmear or surface preparation where applicable, via filling, cure, planarization, copper plating or cap formation, imaging and etching, surface finish, inspection, and assembly validation. The exact sequence depends on the board construction and the approved process.
The DFM review should focus on:
Via fill completeness and void control
Copper cap thickness and surface planarity
Pad-to-via registration and annular geometry
Solderability and solder-joint formation
Thermal stress and interconnect reliability
Inspection coverage and lot traceability
Common VIPPO Problems
| Problem | Possible impact | Prevention or review action |
|---|---|---|
| Incomplete fill or voiding | Weak interconnect or solder-joint defect | Define fill process, acceptance criteria and inspection |
| Non-planar copper cap | Uneven solder volume or open/short risk | Control planarization and cap thickness |
| Misregistration | Reduced pad integrity or clearance | Review stackup, registration budget and artwork |
| Thermal stress | Cracking or reliability loss | Review material CTE, via geometry and thermal cycling |
| Overuse of VIPPO | Higher cost without routing benefit | Compare against fanout, microvia and layer-count alternatives |
VIPPO Cost Drivers
VIPPO cost is affected by via count, pad and via geometry, fill and cap process, board thickness, HDI cycles, material, inspection, yield, prototype quantity, and reliability requirements. A meaningful quotation requires the actual package and stackup data; a per-board estimate based only on the term “VIPPO” can be misleading.
FAQ
What does VIPPO stand for?
VIPPO stands for Via-in-Pad Plated Over.
Is VIPPO the same as via-in-pad?
Not always. VIPPO specifically describes a via-in-pad structure that is filled and plated over to create a flat, solderable pad surface. An open via-in-pad may not meet the same assembly requirements.
Does VIPPO improve signal integrity?
It can shorten or simplify a connection in a dense package area, but the result depends on stackup, reference planes, impedance, return-current paths, and via transitions. VIPPO should be evaluated as part of the complete interconnect design.
Is VIPPO more expensive than a conventional via?
Usually, because it adds fill, planarization, plating, inspection, and process-control requirements. The net cost depends on whether VIPPO reduces layer count, board size, routing complexity, or assembly risk.
What files are needed for a VIPPO quote?
Provide the package drawing, BGA map, pad and via definitions, stackup, fabrication drawing, material requirements, assembly requirements, quantity, schedule, and inspection or reliability requirements.
