Chiplet PCB Design: Co-Design Rules for SI, PI & Thermal

Chiplet PCB design requires coordinated planning between the chip package, PCB stackup, routing, power delivery, and thermal system. Unlike a traditional monolithic processor, a chiplet-based system divides computing, memory, I/O, or other functions across multiple dies and connects them through advanced packaging.

This architecture improves scalability and can allow different chiplet functions to use different process technologies. However, it also creates tighter dependencies between package design and the PCB underneath it.

For PCB engineers, the key challenge is no longer routing the board independently. Package escape, signal integrity, power integrity, thermal performance, HDI structures, and manufacturing capability must be considered together.

What Is Chiplet PCB Design?

Chiplet PCB design refers to the PCB-level design process used in systems that integrate multiple chiplets through advanced package structures.

The highest-density die-to-die connections are normally handled inside the package or substrate. The main PCB still has to provide reliable power, high-speed external interfaces, thermal paths, mechanical support, and manufacturable escape routing.

From Monolithic SoCs to Chiplet Architectures

A traditional monolithic SoC integrates most functions on one large silicon die.

A chiplet architecture separates functions into smaller dies. For example, a system may combine compute chiplets, I/O chiplets, memory interfaces, and accelerators within one package.

This changes the design problem from a single-chip optimization task into a multi-domain system problem.

Why Package and PCB Design Must Be Co-Designed

The package determines how signals and power reach the PCB, while the PCB determines how those connections continue toward memory, connectors, power systems, and other devices.

Package ball maps, BGA pitch, PCB layer count, via structures, impedance targets, and mechanical keep-outs therefore need to be coordinated before the PCB layout is finalized.

Industry co-design workflows increasingly treat die, package, and board as connected design domains rather than independent stages.

How Chiplets Change PCB Design Requirements

Design Factor	Traditional High-End PCB	Chiplet-Based System
I/O density	High	Very high
Data rate	High	Extremely high
Power domains	Several	Often highly distributed
Thermal density	High	Very high
Via technology	Through/blind vias	HDI and microvias may be required
SI analysis	Board-level	Package-to-board channel
PI analysis	Board-level	Die-to-package-to-board
Thermal analysis	Board-focused	Package and board combined

Higher I/O Density

Chiplet packages can expose a large number of high-speed and power connections through dense BGA interfaces.

The PCB must provide a practical fanout strategy without creating excessive routing congestion or compromising power and ground return paths.

Higher Data Rates

Modern AI and networking systems can use interfaces such as PCIe, high-speed SerDes, and 112G-class PAM4 links.

At these data rates, even relatively short PCB traces can contribute meaningful insertion loss, reflection, crosstalk, and timing uncertainty.

More Complex Power Delivery

Different chiplets can operate from different voltage rails and load profiles.

The PCB power distribution network therefore needs to support multiple power domains while minimizing voltage fluctuation and parasitic inductance.

Higher Thermal Density

Chiplets can concentrate significant power within a relatively small package.

The PCB thermal design must provide an effective path from the package into copper planes, thermal vias, heat spreaders, or system-level cooling structures.

Chiplet Package-to-PCB Co-Design

The package-to-PCB interface is one of the most important areas in chiplet board design.

Package Escape and PCB Fanout

The package ball map should be reviewed together with the PCB escape strategy.

Before locking the package interface, engineers should determine:

• BGA pitch
• Escape direction
• Number of required routing layers
• Via diameter
• Via-in-pad requirements
• Power and ground allocation
• High-speed interface locations

If the package is finalized without considering PCB routability, the board may require unnecessary layers or advanced HDI structures.

BGA and Via Strategy

Dense chiplet packages may require:

• Microvias
• Blind vias
• Buried vias
• Via-in-pad
• Stacked or staggered microvias

The correct structure depends on pitch, layer count, reliability requirements, and PCB fabrication capability.

The PCB manufacturer should review these features before the layout is released for production.

Keep-Out and Mechanical Constraints

Mechanical constraints should also be included during co-design.

Package dimensions, heat spreaders, stiffeners, connectors, mounting hardware, and enclosure boundaries can all affect component placement and routing.

A package or PCB change made late in development can therefore create electrical, thermal, and mechanical conflicts simultaneously.

Chiplet PCB Stackup and Material Selection

Layer Stackup

The stackup should be designed around the required signal layers, reference planes, power distribution, HDI structures, and finished board thickness.

High-speed signal layers should have stable reference planes and controlled dielectric geometry.

A symmetric stackup can also help reduce warpage and improve manufacturing consistency.

Low-Loss Dielectric Materials

For high-speed chiplet systems, dielectric loss becomes increasingly important.

Material selection should consider:

• Dk
• Df
• Resin system
• Frequency stability
• Thickness tolerance
• Thermal performance
• Availability

The lowest-loss material is not always the best choice. The material must provide sufficient electrical margin while remaining practical for production.

Copper Roughness

Copper surface roughness contributes to conductor loss, especially at higher frequencies.

For high-speed channels, copper roughness should therefore be considered together with dielectric loss and trace geometry.

HDI and Microvia Structures

High-density package interfaces may require HDI construction to escape dense BGA patterns.

Microvia structures can reduce routing congestion and allow shorter vertical transitions, but they also introduce additional manufacturing and reliability requirements.

For related design considerations, see SLLPCB’s HDI PCB Design Guide.

Signal Integrity Rules for Chiplet PCBs

Controlled Impedance

High-speed chiplet interfaces should use controlled-impedance routing based on the interface specification.

Trace width, dielectric thickness, copper thickness, Dk, and reference-plane geometry all affect characteristic impedance.

Impedance should be validated through stackup calculation and, where required, impedance coupons.

Differential Pair Routing

Differential pairs should maintain controlled geometry throughout the channel.

Important parameters include:

• Trace width
• Pair spacing
• Intra-pair skew
• Layer transitions
• Reference-plane continuity
• Via geometry

Avoid unnecessary routing discontinuities because every transition can introduce additional parasitic effects.

Via Stubs and Transitions

Long via stubs can create resonances and degrade high-speed channels.

Backdrilling, optimized via structures, or alternative layer transitions may be considered when the channel budget requires it.

The decision should be based on channel simulation rather than applying backdrilling automatically to every design.

Crosstalk and Return Paths

High-speed routing should maintain a continuous return-current path.

Avoid routing across reference-plane splits or creating unnecessary parallel coupling between sensitive differential pairs.

Reference-plane changes should include an appropriate return-current transition strategy.

Intel’s board design guidance similarly emphasizes stackup, reference planes, crosstalk control, and return-path continuity in high-speed PCB design.

Power Integrity and PDN Design

Multiple Power Domains

Chiplet systems may contain separate voltage rails for compute, memory, I/O, analog, and other functions.

The PCB power distribution network should define each rail’s current requirement, target impedance, decoupling strategy, and return path.

Decoupling

Decoupling capacitors should be placed according to the power-delivery architecture rather than simply following a fixed placement rule.

Short current loops and low-inductance connections are especially important for high-current, fast-transient loads.

Decoupling may exist across multiple levels, including the die, package substrate, interposer, and PCB.

Power and Ground Planes

Low-impedance power and ground structures provide the foundation for stable power delivery.

Plane geometry, via arrays, copper thickness, and current distribution should be evaluated together.

PDN Simulation

For demanding systems, PDN simulation can identify anti-resonances, impedance peaks, voltage droop, and other potential problems before hardware is built.

The simulation model should include the relevant package and PCB parasitic elements rather than treating the PCB as an isolated power network.

Thermal Management in Chiplet PCB Design

High Power Density

Chiplet architectures can place multiple high-power dies within one package.

This creates a thermal concentration that may exceed the capability of a conventional PCB cooling structure.

Thermal Vias and Copper Areas

Thermal vias can transfer heat from component pads or copper regions toward internal and bottom copper structures.

Large copper areas can also spread heat laterally.

The final structure should consider via density, copper thickness, board thickness, component constraints, and manufacturing capability.

CTE and Warpage

Silicon, package substrates, laminates, copper, and mechanical components have different coefficients of thermal expansion.

Repeated heating and cooling can therefore create mechanical stress.

A balanced PCB stackup, controlled copper distribution, and appropriate material selection can help reduce warpage risk.

Package-to-PCB Thermal Path

Thermal design should not stop at the package boundary.

The thermal path should be evaluated from the chiplet through the package and PCB and finally into the system cooling structure.

This is one reason chiplet systems benefit from package-board thermal co-design rather than independent thermal analysis.

HDI Routing and Manufacturing Considerations

Microvias

Microvias are useful for dense BGA fanout and short vertical connections.

However, microvia diameter, aspect ratio, pad geometry, stacking method, and registration tolerance must be compatible with the selected manufacturing process.

Via-in-Pad

Via-in-pad can provide a compact escape solution for fine-pitch packages.

When used with BGA or other dense components, the filling and planarization process should be clearly specified.

Sequential Lamination

Advanced HDI structures may require multiple sequential lamination cycles.

Additional cycles increase process complexity and should be justified by routing requirements.

Manufacturing Tolerances

A chiplet PCB should not be designed only around nominal geometry.

Engineers should consider:

• Registration tolerance
• Drill tolerance
• Copper thickness variation
• Dielectric thickness tolerance
• Etch compensation
• Via reliability
• Warpage
• Surface finish requirements

IPC provides board design standards covering electrical integrity, signal and power performance, and HDI design considerations.

Chiplet PCB Design Workflow

System and Package Planning

Start by defining:

• Chiplet functions
• Package architecture
• I/O requirements
• Power domains
• Thermal targets
• Mechanical constraints
• External interfaces

Stackup and Constraint Definition

Define the PCB stackup before detailed routing.

Set impedance targets, layer assignments, copper weights, dielectric requirements, via structures, and manufacturing constraints.

Layout and Routing

Place high-speed interfaces, power components, and thermally critical devices first.

Then develop the escape and routing strategy around those constraints.

SI/PI/Thermal Simulation

Perform the appropriate simulations before final design release.

Depending on the system, this may include:

• Channel simulation
• Impedance analysis
• Crosstalk analysis
• PDN simulation
• Thermal simulation
• Mechanical or warpage analysis

DFM and Manufacturing Review

The final layout should be reviewed against the actual PCB manufacturing process.

A design that is theoretically routable may still be difficult to fabricate consistently.

For dense HDI structures, early DFM review can identify problems with microvias, registration, stackup, and fabrication tolerances before production.

See the SLLPCB PCB DFM Review Sequence for a practical review flow.

Prototype Validation

Prototype testing should verify the assumptions made during design.

Depending on the project, validation may include:

• Electrical testing
• Impedance testing
• Thermal testing
• X-ray inspection
• Cross-section analysis
• Assembly inspection
• Functional testing

The results should be fed back into the production design before volume manufacturing.

Chiplet PCB Design Rules Checklist

Design Area	Key Check
Package interface	BGA pitch and escape strategy are compatible
Stackup	Signal and reference layers are properly assigned
Materials	Dk, Df, loss, thermal and availability requirements are met
High-speed routing	Impedance, skew and return paths are controlled
Vias	Stub length and via structures are acceptable
Power	Power domains and decoupling are defined
Thermal	Heat path and thermal expansion are reviewed
HDI	Microvia and via-in-pad structures are manufacturable
DFM	Fabrication tolerances are verified
Testing	SI, PI, thermal and production tests are defined

FAQ

What is chiplet PCB design?

Chiplet PCB design is the process of designing the PCB that supports a chiplet-based system while coordinating package interfaces, routing, power delivery, thermal management, signal integrity, and manufacturing requirements.

Does chiplet design require HDI PCB technology?

Not every chiplet system requires HDI, but dense package interfaces can make microvias, blind vias, or via-in-pad structures necessary for practical escape routing.

Does chiplet PCB design require low-loss materials?

For high-speed interfaces, low-loss materials may be required to maintain sufficient channel margin. The appropriate material depends on data rate, channel length, dielectric properties, copper roughness, and system requirements.

Why is package-to-PCB co-design important?

The package ball map and PCB escape strategy are directly connected. Coordinating them early can reduce routing congestion, unnecessary layers, and late-stage package or PCB changes.

How does chiplet design affect thermal management?

Multiple high-power dies can concentrate heat in a small package. The thermal path therefore needs to be considered across the die, package, PCB, and system cooling structure.

What simulations are useful for chiplet PCB design?

Depending on the system, useful analyses include signal integrity, power integrity, thermal analysis, crosstalk, impedance, and mechanical or warpage analysis.

What PCB manufacturing capabilities may be required?

Depending on package density and performance requirements, chiplet boards may require HDI, microvias, via-in-pad, controlled impedance, low-loss materials, tight registration, backdrilling, and advanced inspection.

Conclusion

Chiplet PCB design is no longer simply a board-routing problem. The package, PCB, power system, thermal path, and manufacturing process influence each other and should be evaluated as one system.

The most important design priorities are package-to-board escape, controlled impedance, continuous return paths, stable power delivery, thermal management, appropriate HDI structures, and manufacturable stackup and material choices.

The best chiplet PCB is not necessarily the one with the most advanced technology. It is the one that provides the required electrical and thermal performance while remaining manufacturable, testable, and reliable at production volume.